A conventional test apparatus will be explained with reference to accompanying drawings. FIG. 1 is a block diagram of a conventional test apparatus for a semiconductor IC for testing semiconductor memories.
The conventional test apparatus comprises: a timing generator 1 for generating timing of a signal for testing a memory 5 under test (hereinafter referred to as "IC under test"); a pattern generator 2 for generating a test pattern, for testing the IC 5 under test, utilizing as an input the timing signal from the timing generator 1; a waveform generator 3 for forming a waveform utilizing as an input the timing signal from the timing generator 1 and the pattern signal from the pattern generator 2; a drive circuit 4 for converting the signal generated in the waveform generator 3 to a voltage; an IC 5 under test which is tested by inputting a signal driven by the drive circuit 4; a signal integration circuit 7 for receiving a signal output from the IC 5 under test and conducting level comparison with an expected value (not shown) utilizing an STRB signal generated by a strobing pulse generator 6 based on the timing signal generated in the timing generator 1; and a logic comparator 8 for conducting logic comparison of a comparison result signal generated in the signal integration circuit 7 with an expected value pattern signal generated in the waveform generator 3 and making a judgement such that, when both the logics agree with each other, the IC is acceptable while, when both the logics disagree with each other, the IC is unacceptable.
In the above test apparatus, an increase in speed and capacity of the IC 5 under test has led to a demand for high speed operation, high timing accuracy, and high processing capability. This test apparatus comprises electronic circuits each comprising a set of a waveform generator 3, a strobing pulse generator 6, and a logic comparator 8, the electronic circuit being constituted by an LSI and provided in a number corresponding to the number of terminals of the IC 5 under test. For example, the above electronic circuit comprises an ECL-G/A which can be operated at ultrahigh speed and of which the delay time is less dependent upon the temperature.
An ECL-G/A, however, for reasons of a small number of gates, large amount power consumption, high cost and the like, had led to drawbacks such as increased cost of the apparatus, increased power consumption of the apparatus, and increased size of the apparatus.
In order to eliminate the above drawbacks, an attempt has been made to adopt CMOS type LSI. For example, a CMOS-G/A is advantageous in that it has many gates (several M gates), low power consumption (about several W), and low cost. On the other hand, in the case of a CMOS-G/A, most of the power consumption is determined by a charge and discharge current for the load capacity, that is, by the product of the load capacity by the operation frequency, causing the ambient temperature of a CMOS-G/A to vary with a change in the operation frequency. For example, since the on-state resistance of the transistor is varied to vary the rise time of the signal, the transmission delay time is likely to become unstable, disadvantageously making it difficult to ensure timing accuracy.
In the test of an IC under test, varying the test operation frequency is unavoidable and, hence, renders the transmission delay time unstable, making it impossible to ensure the timing accuracy, which is a serious problem.
Japanese Patent Laid-Open No. 279874/1992 discloses a technique for solving the above problem using CMOS-G/A. In the technique disclosed in Japanese Patent Laid-Open No. 279874/1992, a dummy circuit is provided in a chip of an LSI constituting a waveform generator and a strobing pulse generator, and this dummy circuit is constructed so as to operate at a frequency which differentially varies relative to the operation frequency of the waveform generator and the strobing pulse generator. Since the waveform generator and the strobing pulse generator and the dummy circuit are operated by signals which are mutually differentially varied, the sum of both the power consumption can be made constant.
Therefore, the temperature of the LSI chip can be always kept constant independently of a change in operation speed, making it possible to avoid a change in delay time,
In the technique disclosed in Japanese Patent Laid-Open No. 279874/1992, a differentially varied signal P.sub.CLK may be as shown in FIG. 2A. Specifically, a timing signal D.sub.B is a timing signal which is fed to the waveform generator 3, the strobing pulse generator 6, and the logic comparator 8, and the timing signal P.sub.CLK is a signal which is fed to the dummy circuit, the frequency of the signal being differentially varied depending upon the frequency of the timing signal D.sub.B.
The value of the differentially varied frequency should be previously described as a part of a test program after a complex calculation involving a test pattern. Alternatively, the test apparatus should be loaded with a complex computing circuit to automatically provide the differentially varied frequency.
An increase in complexity of the function of the IC 5 under test has lead to an increase in complexity of the waveform generated, for example, in the waveform generator 3.
Drawbacks of the technique disclosed in Japanese Patent Laid-Open No. 279874/1992 will be described with reference to FIG. 2B showing an example of operation of a waveform generator. FIG. 2B is a diagram showing any given enlarged section of the test pattern shown in FIG. 2A.
A signal D.sub.B and a signal P.sub.EOR are timing signals in the timing generator 1, a signal P.sub.INK a pattern signal in the pattern generator 2, and a signal O.sub.OUT a signal output from the waveform generator 3 and input into the drive circuit 4. In the drawing, each of numerals 1 to 6 represents one clock cycle.
In the example shown in the drawing, the signal D.sub.B is set by two sets of timing preset values, one set consisting of values, 1, 2 and 6 with the other set consisting of values 3, 4 and 5. Thus, a plurality of timing preset values can be set in clock cycles.
A signal P.sub.EOR is a signal which conducts exclusive "OR" operation of the waveform of the signal D.sub.S add qualification, and a signal P.sub.INH is a signal which further ANDs the results of the above logical operation. ##EQU1##
According to "Gate Array, " a data book published by NEC Corp., the consumed power of a CMOS6/6A family is calculated, for example, by the following equation 2. EQU Total consumed power P.sub.D =.SIGMA.P.sub.DCELL +.SIGMA.P.sub.D1 +.SIGMA.P.sub.D0 ( 2)
wherein EQU .SIGMA.P.sub.DCELL =consumed power of internal cell (.mu.W)=.SIGMA.(8*f*Cell*A) . . . A: constant EQU .SIGMA.P.sub.DI =consumed power of input buffer (.mu.W)=.SIGMA.(46*f*Buffer ) EQU .SIGMA.P.sub.DO =consumed power of output buffer (mW)=.SIGMA.(0.23+0.016(Cl+34)*f+Pconst)*Buffer)
wherein
f: operation frequency (Mhz) PA1 Cl: load capacity (pF), and PA1 Pconst: steady-state consumed power. PA1 CMOS type LSIs in a number corresponding to the number of terminals of the semiconductor IC, PA1 each said LSI having a waveform generator, a strobing pulse generator, and a logic comparator, PA1 at least one of the waveform generator, the strobing pulse generator, and the logic comparator being paired as a functional block with a thermal control circuit, PA1 the power consumption of the thermal control circuit being regulated by the output operating frequency of the functional block.
As described above, most of the consumed power of a CMOS-G/A is a charge and discharge current for a load capacity during operation. The approximate consumed power is determined by the load capacity and the operation frequency.
In this case, for the signal D.sub.B shown in FIG. 2, three charges and three discharges are performed in 1-2, 3-4, and 5-6. On the other hand, the signal O.sub.OUT performs six discharges and five charges in close relationship with the signal P.sub.INH.
Thus, the relationship between the signal D.sub.B and the signal O.sub.OUT is in close relationship with the equation 1 determined by the test problem. Further, the consumed power of .SIGMA.P.sub.D0 output buffer is greatly influenced by the operation frequency of the signal O.sub.OUT and the number of output buffers and occupies a large proportion of the total consumed power.
Therefore, the technique disclosed in Japanese Patent Laid-Open No. 279874/1992, that is, the technique wherein "when the frequency of the timing signal D.sub.B is changed from f1 to f2 (f1&lt;f2), for example, the operation frequency of the signal P.sub.CLK given to the dummy circuit 9 constituted by gate arrays cascaded in a suitable number of stages is differentially changed from f2 to f1," has the following problem.
Specifically, the differentially varied signal P.sub.CLK is not determined by the frequency of the timing signal D.sub.B alone and should be in close relationship with the equation 1 determined by the test problem as in the signal O.sub.OUT.
Further, in the technique disclosed in Japanese Patent Laid-Open No. 279874/1992, the circuit size of the dummy circuit is so large (30 to 50%) that the utilization efficiency of the gate array circuit is low.
Furthermore, the technique has a problem that in some arrangement of the dummy circuit, the heat balance is broken and the sum of power consumption cannot be made constant, resulting in unstable transmission delay time, which makes it impossible to ensure the timing accuracy.